Who we are
Lucid Circuit is a Santa Monica-based company developing energy-efficient signal processing
and machine learning platforms for aerospace applications. Through significant improvements
of onboard processing capabilities, spaceborne and airborne applications can see reduced
communication bandwidth requirements and reduced latency for delivery of analytics
approaching real-time. AstrumTM is Lucid Circuit’s line of radiation-tolerant and energy-efficient processors for reliable high-performance cognitive applications in edge devices.

Who we’re looking for and what your responsibilities will be

Join Lucid Circuit and help develop aerospace-focused, cognitive edge-resilient processors and
tools. As a member of the hardware microelectronics team, you will be responsible for Cell,
Block, section layout and verification in mixed-signal designs. You should have proven
experience in creating layout methodologies, flows, and tape-out procedures. This is an
opportunity to work with subject matter experts in custom tooling for novel architectures,
compilers, statistical learning, microelectronics, semiconductors and radiation physics. A broad
technical background is central to this unique opportunity to solve challenging optimization
problems at Lucid Circuit.

U.S. Citizenship or permanent resident status is required for this position.

Responsibilities:

  • Manage test chip planning, layout of bit cell arrays, periphery layout structures (up to macro and chip level).
  • Custom analog/digital and memory, plus PD (P&R) in mixed-signal designs.
  • Experience working on PLL, VCO, Voltage Regulator, Bandage, Baseband Filter, Loop
  • Filter, TX/RX Drivers, PI blocks.
  • Full custom RF/Analog, Mixed-Signal Layout Techniques
  • Experience with DDR, TSMC 45nm, 28nm, 20nm, 16FF, 11LM, SAMSUNG 14LPE, 11LPE, 10LPE, 8LPE, 7LPE.
  • Graphics Tools used: Cadence VXL, Calibre, Synchronicity.
  • Conducting weekly progress meetings with layout and engineering while maintaining project layout schedule.
  • Responsible for all post-processing of test chip DBs, all documentation, and tape-out reviews in preparation for tape-out/data release.
  • Additional experience working across design groups with 3D stack chip tech (TSV), and POG test structures (passive on glass).
  • Current, hands-on experience with TSMC, Samsung, UMC, Global Foundry PDKs and TO flows, working with 180nm, 45/40nm, 28LP/HPM, 20SOC, 16FF and 14FF tech nodes.

Benefits and Perks

  • Excellent compensation package commensurate with experience.
  • Premier office location in Santa Monica.
  • A team that will challenge you intellectually and creatively.

Lucid Circuit is an Equal Opportunity Employer. Employment decisions are made without regard
to race, color, religion, national origin, gender, sexual orientation, gender identity, age, physical
or mental disability, genetic factors, military/veteran status or other characteristics protected by
law.

To apply, please email your resume to contact@lucidcircuit.com.